4.5.9 Cyclic Code Generation
To generate a systematic cyclic code, the data word is first shifted right by (n−k) bits and then divided by the generator polynomial. In hardware, this is implemented using shift registers and modulo-2 feedback adders.
Figure 4.14 illustrates the generation of a systematic cyclic code. During the first k shifts, Switch 1 is closed to shift the k data bits into the (n–k) stages of the shift register while simultaneously outputting them through Switch 2 directly to the output. During the next (n–k) shifts, Switch 1 opens and Switch 2 redirects the parity bits generated by the feedback logic, to the output, thus producing the complete systematic codeword.
